As typical prior-art examples of a flash EEPROM (Electrically Erasable and Electrically Programmable Read Only Memory), a unit memory cell structure is shown in FIG. 3b of the JP Patent Kokai publication Sho 61-127179 (1986), while the operation of the unit memory cell is described in, for example, in Gautum Verma & Neal Mielke, "RELIABILITY PERFORMANCES OF ETOX BASED FLASH MEMORIES", 1988 IEEE/IRPS, pages 158 to 166.
The method for programming and erasing data in a memory array comprised of memory cells is shown for example in VIRGIL NILES KYNETT et al, "An In-System Reprogrammable 32K.times.8 (CMOS Flash Memory", Journal of Solid State Circuit October, 1988 Vol. 1, 23 No. 5 pages 1157 to 1163. These prior-art technique are now described by referring to FIGS. 7 and 8A-8B.
FIG. 7 shows a unit memory cell in cross-section. The memory cell is made up of a drain diffusion layer 502 formed by a n.sup.+ diffusion layer on the surface of a p-type semiconductor substrate 501, a source diffusion layer 503 having a double structure of an n.sup.+ diffusion layer 503-1 wrapped by an n.sup.- diffusion layer, 503-2, a floating gate 505 provided on a tunnel insulating layer 504 covering a channel region between the source and the drain, and a control gate 507 provided thereover with intervention of an insulating layer 506.
Referring to FIGS. 8A and 8B, operation of the memory cell is explained. For writing or programming data, the source and the substrate are grounded and high voltages Vg and V.sub.D (Vg&gt;V.sub.D) are respectively applied to the control gate and the drain to inject electrons generated by impact ionization near the drain into the floating gate, as shown in FIG. 8A.
For erasing the data, the control gate and the substrate are grounded and the drain is kept open. On the other hand, a (positive) high voltage V.sub.pp is applied to the source, as shown in FIG. 8B. As a result, electrons can be transported from the floating gate to the source due to tunneling effect. The n.sup.- diffusion layer 503-2 is provided in the source in order to prevent avalanche breakdown from being generated between the source and the substrate even if a voltage sufficient to produce tunnel emission is applied to the source.
In an actual memory device, a number of such memory cells are arranged in a matrix to provide a memory cell array, as shown in FIG. 9. In this memory device, the control gates of the memory cells of the same rows are connected in common to an associated one of a plurality of word lines 508, the drains of the memory cells of the same columns are connected in common to an associated one of a plurality of bit lines 509, and the sources of the memory cells of the same columns are connected in common to an associated one of a plurality of source lines 510. The word lines 508 and the bit lines 509 are connected to a row decoder 511 and a column decoder 512, respectively. The source lines 510 are connected in common to a circuit mode, supplied via a selector switch 513 with the ground during read out and writing of the memory cell and with an erase voltage from a generator 514 during erasure of the memory cells.
The memory cell array also includes a read control circuit 515, and a write control circuit 516 and a erase control circuit 517 for performing data reading, data writing and erasing operations. Output control signals of the read out control circuit 515, the write control circuit 516 and the erase control circuit 517 are supplied to the row decoder 511 and the column decoder 512.
The operation of the memory cell array shown in FIG. 9 is now explained. During writing in the memory cell, the source lines 510 are connected to the ground via the selector switch 513 and a write control circuit 516 operates to write data in the memory cell MC selected by setting a selected bit line and a selected word line to a high level voltage by the column decoder 512 and the low decoder 511, respectively.
During read out, as during writing, the source lines 510 are connected to the ground and the read out control circuit 515 operates for setting a selected bit line and a selected word line to a read-out voltage (.about.5 V) by the column decoder 512 and the row decoder 511 to read out the selected memory cell.
During erasure of the memory cell, the source lines 510 are connected via the selector switch 513 to the erase voltage generator 514 and the erase control circuit 517 is activated for setting the source lines 510 and the word lines to a high voltage (.about.12 V) and to the ground potential, respectively, for erasing all the memory cells in their entirety.
With the conventional flash EEPROM, all the bits are written before erasing for setting the threshold voltage of all the memory cells substantially to the same value. In order to prevent the occurrence of overerasure of the memory cells, the erasure is then carried out in the short interval, little by little by dividing the erase time into small fractions of short internal. The threshold voltage of the memory cells are verified after each erase step and the erase operation is stopped when an optimum threshold voltage is reached.
The reason such erase procedure is adopted is that overerasure leads to infeasibility of correct data read out. Memory cell erasure is explained hereinbelow by referring to FIGS. 10 and 11.
FIG. 10 is a graph showing the relation between the memory cell threshold voltage V.sub.TM and the erase time. As may be seen from the graph of FIG. 10, should the erase time to exceed a certain value t.sub.o, the memory cell threshold voltage, set in the initial state to a value on the order of the threshold voltage of 5 V, assumes a negative value. That is, the memory cell is in a state of so-called depletion status in which it is turned on even when a gate is of a ground potential.
It is now supposed that, with the memory cell array shown in FIG. 9, a memory cell array H is overerased. If then data is written into a memory cell I and subsequently read out, no current will flow between the drain and the source of the selected memory cell I. However, the current flows between the drain and the source of the non-selected memory cell H, so that the current flows through the leftmost bit line. For this reason, the off-bit memory cell I would be erroneously detected as being on-bit. Thus there should be no overerasure during memory cell erasure.
Referring to FIG. 11, the reason the writing of all bits prior to erasure is required is now explained.
FIG. 11 is a graph showing erasure characteristics of a memory cell in a written state and a memory cell in the non-written state. In a flash EEPROM memory cell array, a fraction of the memory cells are usually in the written state, while the remaining memory cells are in the non-written state. Since the erasure speed of the written memory cell is substantially equal to that of the non-written memory cell, an overerasure is produced in the non-written memory cell (see the lower line in FIG. 11) of the written memory cell is insufficiently erased, unless all the bits ape set to the written state before erasure of all of the bits.
The above-described prior art flash EEPROM has the following disadvantages.
First, the source and drain have asymmetrical structures, such that one mope mask needs to be used, thus raising production cost.
Second, a higher voltage (.about.12 V) is required for driving the memory cell.
The recently employed high performance fine-sized CMOS transistors, such as those having a gate length of 0.8 .mu.m or less and a transconductance value of 400 or above cannot maintain the breakdown voltage as required. Thus, in order to cope with high voltages, high breakdown voltage transistors having a dedicated gate insulating layer or source/drain structure need to be employed, so that the number of masks used fop producing such components is increased.
Specifically, in the case of an oxide layer, an electric field applied to the gate insulating layer is set to less than or equal to a maximum of 4 MV/cm, above which a tunneling current starts to flow. For example, the thickness of the oxide layer is set to a value on the order of 300 Angstrom (30 nm) if a memory cell is to be driven at a voltage of 12 V. For an voltage of 5 V, the thickness of the oxide layer is set to a value on the order of 130 Angstrom (13 nm). For a source drain structure of the high breakdown voltage transistor, a lower impurity concentration is employed than for the ordinary source drain structure.
That is, if a conventional flash EEPROM is to be formed on an integrated circuit made up of high-performance fine-sized CMOS transistors, a higher voltage is required for driving the memory cell. For this reason, in the case of the high-performance fine-sized integrated circuit, it is necessary to provide dedicated high breakdown voltage transistors, while an increased number of the masks need to be employed for producing them, with consequent rise in the production cost.
Third, for preventing an overerasure during erasing, data is written in all the bits before erasure. Besides, for maintaining the threshold voltage of a memory cell to be erased at a proper level, the memory cell threshold voltage needs to be verified each time the erasure is executed for a pre-set short interval of time, as a result of which the erase procedure becomes complex and the chip area is increased due to the increased number of control circuits while the time required for erasure testing is increased with a consequent rise in the production cost.
For obviating the above-mentioned second drawback, there is disclosed in JP Patent Kokai Hei 3-79884 (1991) and JP Patent Kokai Sho 56-129374 (1981) means for lowering the memory cell operating Voltage. Such voltage lowering means is now explained by referring to FIG. 12.
In FIG. 16, there is known a method for erasure comprising generating the avalanche breakdown state between a semiconductor substrate 501 and a drain diffusion layer 502 and applying a negative voltage to a control gate 507 for injecting holes into a floating gate 505. A p.sup.+ region 518 higher in concentration than the substrate 501 is provided in the vicinity of the drain 502 for producing avalanche breakdown at lower voltage in order to effect erasure.
However, with the above method in which the p.sup.+ region 518 higher in concentration than the substrate 501 is provided in the vicinity of the drain 502 and a lower voltage is applied to the drain to produce avalanche breakdown between the drain and the substrate, while the negative voltage is applied to the control gate 507 to inject holes into the floating gate, the number of peripheral control/circuits is increased for applying both the positive and negative voltages, while the circuit area is increased with a rise in the production cost. In addition, since the p.sup.+ region 518 is selectively formed only neap the drain 502, the number of the masks is similarly increased due to the asymmetric structure.
For obviating the above-mentioned third drawback in the conventional flash EEPROM, there are proposed in JP Patent Kokai Sho 64-46297(1989) a method and an apparatus for self limiting electrical erasure of a single-transistor-floating-gate cell. With such structure, drain potential is fed back during erasure via a feedback amplifier to a control gate, and an erase voltage is applied to a source, with electrons penetrating from the floating gate to the source under tunneling effect, wherein the drain potential is raised proportionately as electrons are discharged from the floating gate. Such rise in potential is detected to stop the erasure.
As another means for obviating the above-mentioned third drawback, the source, the control gate and the substrate are grounded, and a voltage just high enough to turn the channel on is applied to the drain, so that holes or electrons generated by impact ionization neap the drain are injected into the floating gate, as disclosed in YAMADA et al "A Self-Converence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", IEDM '91, pages 307 to 309. With such method, even if overerasure occurs in a memory cell, rewriting is made to make the overerased memory cell to an enhancement state, i.e., to return to a positive threshold voltage state, while threshold voltages of plural transistors in the erased state are made uniform. Representative data of threshold voltage variation with respect to the re-write mechanism and the stress time by this method are shown in FIG. 13.
FIG. 17 shows the threshold voltage versus the drain stress time, with different initial threshold voltages as parameters. The control gate and the source are grounded and 6 V is applied to the drain. In FIG. 13, there is no shift to a stable state with an initial threshold voltage V.sub.TM of 3 V, but the lower two threshold voltages with the source grounded (with initial threshold voltages V.sub.TM of 1 V and -1 V) are shifted to reach a stable state. YAMADA et al state that this would be ascribable to the channel electron induced avalanche hot carrier(CEIA-HC) injection.
JP Patent Kokai Sho 64-46297 (1989) discloses stopping the erase process by detecting rise in the drain voltage for preventing overerasure. However, it is indispensable to write all bits before erasure thus protracting the erasure sequence with rise in the cost in erasure testing so that the chip area is increased by an increased control circuitry and hence the production cost is increased.
With a method shown in IEDM '91 pages 307 to 309, in which overerased cells are returned to a predetermined state by re-writing, writing in all bits before erasure is not required. However, since channel electron induced avalanche hot carrier injection (CEIA-HC injection) is performed after erasure by Fowler-Nordheim (F-N) tunneling injection, a two-steps of erase processes are required and a problem still exists that significant reduction in cost is required for erasure testing. With the technique disclosed in IEDM '91 pages 307 to 309, the verification of the threshold voltage after erasure is carried out in practice.